This invention relates to the field of computer logic simulation.
Techniques are known for simulating the operation of a proposed logic design. One such technique is incorporated into the computer simulation software sold under the trademark MAX-PLUS available from Altera Corporation of San Jose, Calif. With reference to FIG. 1, a typical computer logic simulation technique proceeds by initially providing a logic design in the form of a schematic or netlist stored in a file (10) and converting the netlist by means of a logic compiler (12) into a simulator logic netlist (14) that is used by a logic simulator (15). A set of simulation input vectors (16) is also provided to the logic simulator (15), which reads the simulator logic netlist (14) along with the simulated input vectors (16) and "simulates" the operation of the logic design by propagating logic levels through the logic primitives in order to generate a set of output vectors (18), which are the simulated outputs of the logic design. This process has been found to be exceedingly useful in the field of logic design, particularly for complex circuits. However, this process can be very time consuming (particularly for complex circuits), since the simulator must continually interpret a very large netlist as it propagates the logic levels of the design.